The present disclosure relates to metal semiconductor alloy structures for providing low contact resistance and methods of forming the same.
Metal semiconductor alloys such as metal silicides, metal germanides, metal germano-silicides reduce contact resistance between a metal structure such as a metal contact via structure and a semiconductor region such as a source region, a drain region, and a gate conductor line. Formation of metal semiconductor alloys requires an interdiffusion between a metal and a semiconductor material. Typically, the metal is provided as a metal layer, which is deposited after deposition of a dielectric material layer overlying a semiconductor layer and formation of holes within the dielectric material layer to expose the semiconductor material on the top surface of the semiconductor layer. The interface between the metal layer and the underlying semiconductor material is subjected to an anneal at an elevated temperature, typically from 400 degrees Celsius to 700 degrees Celsius, to effect the interdiffusion of the metal and the semiconductor material.
The interdiffusion of the metal and the semiconductor material is self-limiting at a given anneal temperature. Thus, the volume of the metal semiconductor alloy formed by the anneal is limited by the area of the contact between the metal layer and the underlying semiconductor material. As the dimensions of semiconductor devices scale down, the total area available for forming a metal semiconductor alloy per contact is reduced in proportion to the square of the rate of scaling for a linear dimension because the area of contact is scaled in two dimensions. Thus, the contact resistance of a metal semiconductor alloy region between a metal contact via and an underlying semiconductor region becomes significant with the scaling of semiconductor devices. In other words, the reduction in the available area per contact limits the volume of a metal semiconductor alloy region that can be formed, and thereby raises the contact resistance of the metal semiconductor alloy region with the scaling down of device dimensions. However, a high contact resistance of a metal semiconductor alloy region adversely impacts device performance by introducing extra parasitic resistance.